JPS5776876A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5776876A
JPS5776876A JP15206680A JP15206680A JPS5776876A JP S5776876 A JPS5776876 A JP S5776876A JP 15206680 A JP15206680 A JP 15206680A JP 15206680 A JP15206680 A JP 15206680A JP S5776876 A JPS5776876 A JP S5776876A
Authority
JP
Japan
Prior art keywords
layer
poly
etched
oxide film
plasma
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15206680A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0142147B2 (en]
Inventor
Kazuhiro Komori
Jun Sugiura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP15206680A priority Critical patent/JPS5776876A/ja
Publication of JPS5776876A publication Critical patent/JPS5776876A/ja
Publication of JPH0142147B2 publication Critical patent/JPH0142147B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Non-Volatile Memory (AREA)
JP15206680A 1980-10-31 1980-10-31 Manufacture of semiconductor device Granted JPS5776876A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15206680A JPS5776876A (en) 1980-10-31 1980-10-31 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15206680A JPS5776876A (en) 1980-10-31 1980-10-31 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5776876A true JPS5776876A (en) 1982-05-14
JPH0142147B2 JPH0142147B2 (en]) 1989-09-11

Family

ID=15532303

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15206680A Granted JPS5776876A (en) 1980-10-31 1980-10-31 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5776876A (en])

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59161874A (ja) * 1983-02-23 1984-09-12 テキサス・インスツルメンツ・インコ−ポレイテツド 浮遊ゲ−トメモリおよびその製造方法
JPS6273774A (ja) * 1985-09-27 1987-04-04 Toshiba Corp 半導体記憶装置の製造方法
JPS63228670A (ja) * 1987-03-18 1988-09-22 Hitachi Ltd 半導体集積回路装置の製造方法
USRE34535E (en) * 1983-02-23 1994-02-08 Texas Instruments Incorporated Floating gate memory with improved dielectric

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59161874A (ja) * 1983-02-23 1984-09-12 テキサス・インスツルメンツ・インコ−ポレイテツド 浮遊ゲ−トメモリおよびその製造方法
USRE34535E (en) * 1983-02-23 1994-02-08 Texas Instruments Incorporated Floating gate memory with improved dielectric
JPS6273774A (ja) * 1985-09-27 1987-04-04 Toshiba Corp 半導体記憶装置の製造方法
JPS63228670A (ja) * 1987-03-18 1988-09-22 Hitachi Ltd 半導体集積回路装置の製造方法

Also Published As

Publication number Publication date
JPH0142147B2 (en]) 1989-09-11

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